1. Field of the Invention
The present invention relates to a digital radio communication system capable of changing a transmission capacity mode in accordance with a bit error rate.
2. Description of the Related Art
Generally, in a digital radio communication system, bit errors often occur due to fading or the like. If a bit error rate (BER) is increased, the data transmission rate is reduced to decrease the bit error rate.
In short, when the bit error rate rises beyond a permissible level, it will be no longer possible to accurately transmit information. Therefore, various techniques have been proposed to date in an attempt to improve the modulation system and the error correction method in order to reduce data against degradation due to errors when the bit error rate is raised. Additionally, various data protection features have been developed to protect data from errors.
However, no method has been developed to date that can perfectly prevent bit errors from occurring and correct errors contained in data. Therefore, there is a strong need for a system that can efficiently and accurately detect any change in the bit error rate and adopt an adequate transmission rate that can appropriately cope with the detected bit error rate.
In a first prior art digital radio communication system where a quadrature amplitude modulation (QAM) system is used (see JP-A-3-13145), the current level of modulation is switched to a lower level when the number of input signals is smaller than a predetermined number of signals.
In the above-mentioned first prior art digital radio communication system, however, a plurality of modulation circuits and a plurality of demodulation circuits are required, which makes the system complex. Also, since the modulation level is changed only when the number of signals to be transmitted-is changed, the degradation of the line quality of the transmission path cannot be compensated for.
In a second prior art digital radio communication system (see JP-A-6-26356), a large capacity modulation circuit (demodulation circuit) and a small capacity modulation circuit (demodulation circuit) are provided on both the transmission side and the reception side, the large capacity modulation circuit (demodulation circuit) and the small capacity modulation circuit (demodulation circuit) are selected in accordance with the line quality.
Even in the above-mentioned second prior art digital radio communication system, a plurality of modulation circuits and a plurality of demodulation circuits are required, which makes the system complex.
Furthermore, with any of the above-mentioned prior art digital radio communication systems, a switching command is not issued simultaneously to the stations that are communicating with each other but the switching control operation has to be initiated individually for each of the stations. As a result, since the current modulation/demodulation system itself has to be switched to another, the time consumed before the signal transmission is resumed after the switching operation will be enormous.
It is an object of the present invention to provide a simply-constructed digital radio communication system capable of changing a transmission capacity mode for compensating for the degradation of the line quality.
Another object is to be able to simultaneously carry out the switching operation of transmission capacity modes in a plurality of stations.
According to the present invention, in a digital radio communication system for wireless bidirectional communication between a master station and a slave station, each of the master station and the slave station includes an antenna, a subscriber interface, a first signal processing circuit for converting a first continuous data signal from the subscriber interface into a first burst digital signal and allocating it to a first predetermined time slot, a single modulation circuit for modulating the output signal of the signal processing circuit and transmitting a modulated signal to the antenna demodulation circuit for demodulating a signal from the antenna and generating a second burst signal, and a second signal processing circuit for converting the second burst digital signal of a second predetermined time slot into a second continuous data signal and transmitting it to the subscriber interface. Also, the master station further includes a bit error rate monitoring circuit for monitoring a bit error rate in the demodulated signal a master transmission capacity mode control circuit for controlling a transmission capacity mode of the master station in accordance with the bit error rate, and a transmission capacity mode multiplexing circuit for multiplexing the transmission capacity mode of the master station onto the first digital signals. Further, the slave station includes a transmission capacity mode demultiplexing circuit for extracting the transmission capacity mode of the master station, and a slave transmission capacity mode control circuit for controlling a transmission capacity mode of the slave station in accordance with the transmission capacity mode of the master station.
Thus, since each station includes a single modulation circuit, the system can be simply constructed.
Also, a delay circuit is connected between the transmission capacity mode determining circuit and the master transmission capacity mode control circuit, thus simultaneously changing the transmission capacity mode in the master station and the slave station.